A typical example of the semiconductor memory device of the type having read only memory cells and random access memory cells is illustrated in FIG. 1 of the drawings. The semiconductor memory device illustrated in FIG. 1 comprises a plurality of memory cells 1 to 6 arranged in rows and columns, eight data lines extending in column directions, eight complementary data lines each paired with each of the data lines to form a data line pair, a plurality of word lines extending in row directions, and eight read-write buffer circuits each associated with each data line pair. The memory cells 1 to 3 are specified by address "m" and the memory cells 4 to 6 are also specified by address "n". In FIG. 1, only three of the data lines are designated by reference numerals 7, 8 and 9 together with the three complementary data lines 10, 11 and 12. Only one of the read-write buffer circuits 13 is shown in association with the data line 7 and the complementary data line 10. All of the data lines 7 to 9 and all of the complementary data lines 10 to 12 are coupled at one ends thereof to respective source-drain paths of gate transistors 14 to 19 which in turn is coupled to a source of positive voltage 20, and the gate transistors 14 to 19 are formed by p-channel type MOS field effect transistors, respectively. The data lines 7 to 9 are coupled at the other ends thereof to a multi-bit data bus 21 and inverter circuits 22 to 24 intervene between the other ends of the data lines 7 to 9 and the other ends of the complementary data lines 10 to 12, respectively. In this example, the data lines 7, 8 and 9 propagate bits "7", "6" and "0", respectively. All of the gate transistors 14 to 19 have respective gate electrodes commonly coupled to a signal line 25 where a precharge signal PC of an active low level appears so that the source of positive voltage 20 charges up all of the data lines 7 to 9 and the complementary data lines 10 to 12 in the presence of the precharge signal PC of a ground voltage level.
The memory cells consists of random access memory cells and read only memory cells mixed with the random access memory cells. In detail, the memory cells 1, 3 and 5 are the random access memory cells but the memory cells 2, 4 and 6 are the read only memory cells. Each random access memory cell such as, for example, 1 comprises two memory nodes 26 and 27, a series combination of a p-channel type MOS field effect transistor 28 and an n-channel type MOS field effect transistor 29 capable of providing a conduction path between the source of positive voltage 20 and a ground terminal, a series combination of a p-channel type MOS field effect transistor 30 and an n-channel type MOS field effect transistor 31 capable of providing a conduction path between the source of positive voltage 20 and the ground terminal, and two n-channel type MOS field effect transistors 32 and 33 capable of providing respective conduction paths between the memory nodes 26 and 27 and the data line pair. The MOS field effect transistors 28 and 29 have respective gate electrodes commonly coupled to the memory node 27 so that the MOS field effect transistors 28 and 29 are complementarily shifted between on-states and off-states to put a positive high voltage level or the ground voltage level on the memory node 26. Similarly, the MOS field effect transistors 30 and 31 have respective gate electrodes commonly coupled to the memory node 26 so that the MOS field effect transistors 30 and 31 are also shifted between on-state and off-state to put the complementary voltage level on the memory node 27. The two n-channel MOS field effect transistors 32 and 33 have respective gate electrodes commonly coupled to one of the word lines 34 and the word line 34 is coupled to the output node of an AND gate 35 which has two input nodes applied with the precharge signal PC and a selecting signal SC fed from a row decoder circuit ( not shown ). Then, when the selecting signal SC of the positive high voltage level is supplied to one of the input nodes of the AND gate 35 after recovery of the precharge signal PC, the AND gate 35 produces an output signal of the positive high voltage level which is applied to the respective gate electrodes of the n-channel type MOS field effect transistors 32 and 33, so that the n-channel type MOS field effect transistors 32 and 33 concurrently turn on to allow an external device to access a bit of data information in the form of complementary voltage levels stored in the memory nodes 26 and 27.
On the other hand, each read only memory cell comprises an n-channel type MOS field effect transistor 36 capable of providing a source-drain path between one of the data line and the complementary data line and the ground terminal and the n-channel type MOS field effect transistor 36 has a gate electrode coupled to one of the word lines. Namely, the read only memory cell such as the cell 2 provides a conduction path between the data line 8 and the ground terminal and, on the other hand, the read only memory cell such as the cell 4 provides a conduction path between the complementary data line 10 and the ground terminal. The read only memory cell thus arranged pulls down the voltage level on either of the paired data lines so that a bit of data information stored therein is decided by detecting the voltage levels on the paired data lines.
All of the read-write buffer circuits incorporated in the semiconductor memory device illustrated in FIG. 1 are similar in circuit arrangement to one another so that description will be focused on the read-write buffer circuit 13, only. The read-write buffer circuit 13 comprises a latch circuit consisting of two NAND gates 37 and 38, two n-channel type MOS field effect transistors 39 and 40 and two p-channel type MOS field effect transistors 41 and 42, an output buffer circuit 43, and two input buffer circuits 44 and 45. The latch circuit is operative to store a bit of data information in the form of complementary voltage levels appearing on the data line and the complementary data line 7 and 10, respectively. The buffer circuit 43 has a control terminal applied with a read control signal RD and the buffer circuit 43 is operative to transfer the bit of data information stored in the latch circuit to the data bus 21 in the presence of the read control signal RD. On the other hand, the input buffer circuits 44 and 45 are activated by a two-input AND gate supplied with a write control signal WR and a timing clock signal CLK and are operative to transfer a bit of data information in the form of complementary voltage levels fed from the data bus 21 to the data line 7 and the complementary data line 10, respectively.
As to the memory cells 4 to 6, they are associated with a work line 47 which is supplied with an activation signal of the positive high voltage level from an AND gate 48.
Now, description will be hereinunder made for a write-in operation and two read-out operations on the assumption that memory cells of the address "m" store a data information consisting of a string of bits designated by letter "m" in FIG. 2 and that the memory cells of the address "n" store a data information consisting of a string of bits designated by letter "n" in FIG. 2. As will be understood from the FIG. 2, the read only memory cells 2, 4 and 6 respectively store bits "0", "1" and "0". M7 and M5 to M0 represent the respective bits of data information stored in the random access memory cells of the address "m" and the N6 to N1 also represent the respective bits of data information stored in the random access memory cells of the address "n". Each of the bits stored in the random access memory cells of both of the addresses "m" and "n" is either logic "0" or "1". When an external control device such as a microprocessor accesses the memory cell 1 to read-out the bit of data information, the microprocessor supplies the semiconductor device illustrated in FIG. 1 with an address signal representing the address m together with some control signals such as, for example, a chip enable signal. With the control signals, a control circuit (not shown) incorporated in the semiconductor memory device produces the precharge signal PC of the active ground voltage level so that all of the gate transistors 14 to 19 turn on to provide the conduction paths between the source of positive voltage 20 and the respective data lines 7 to 9 and the complementary data lines 10 to 12. The selecting signal SC has been in the high voltage level in the presence of the address signal representing the address "m", then, after recovery of the precharge signal PC, the AND gate 35 allows the word line 34 to go up to the active high voltage level. With the active high voltage level on the word line 34, all of the n-channel type MOS field effect transistors with the gate electrodes coupled to the word line 34 turn on. The n-channel type MOS field effect transistors 32 and 33 turn on to couple one of the data line 7 and the complementary data line 10 to the ground terminal depending upon the bit of data informtion M7, then a difference in voltage level which forms complementary voltage levels appears between the data line 7 and the complementary data line 10. When the timing clock signal CLK goes up to the positive high voltage level, the complementary voltage levels are latched by the latch circuit through the n-channel type MOS field effect transistors 39 and 40 in on-states. In this example, when the bit M7 of logic "0" is stored in the random access memory cell 1, the n-channel type MOS field effect transistor 31 is turned on to discharge the positive electric charges supplied from the source of positive voltage 20, thereby putting the ground voltage level and the positive high voltage level on the data line 7 and the complementry data line 10, respectively. On the other hand, if the random access memory cell 1 stores the bit M7 of logic "l", the complementary data line 10 is discharged through the n-channel type MOS field effect transistor 29. After the bit M7 is stored in the latch circuit, the bit M7 is read out to the data bus 21 through the output buffer circuit 43 in the presence of the read control signal RD.
In write-in operation, when the AND gate 35 allows the word line 34 to go up to the positive high voltage level, all of the n-channel type MOS field effect transistors including the transistors 32 and 33 turn on, again. With the write control signal WR and the timing clock signal CLK concurrently in the positive high voltage level, a voltage level appearing on the data bus 21 are transferred to the data line 7 through the input buffer circuit 45 and the inverse thereof is fed from the inverter circuit 22 to the complementary data line 10 through the input buffer circuit 44. The n-channel type MOS field effect transistors 32 and 33 have been turned on so that a new data bit consisting of the voltage level on the data line 7 and the inverse thereof on the complementary data line 10 passes through the n-channel type MOS field effect transistors 32 and 33 and reaches the memory nodes 26 and 27. If the new bit is equal in logic level to the previously stored bit, the series combination of the MOS field effect transistors 28 and 29 and the series combination of the MOS field effect transistors 30 and 31 are not shifted, however if the new bit is different in logic level from the previously stored bit, the MOS field effect transistors 28 and 29 and the MOS field effect transistors 30 and 31 are complementarily shifted to change the voltage levels on the memory nodes 26 and 27, respectively.
If the microprocessor needs to access the read only memory cell 4 to read out the bit of the data information, the microprocessor supplies the semiconductor memory device with an address signal representing the address "n" together with the control signals. In the first stage of the read-out operation, the precharge signal PC goes down to the active ground level so that the gate transistors 14 to 19 turn on to allow the source of positive high voltage 20 to charge up the data lines 7 to 9 and the complementary data lines 10 to 12. Subsequently, when a selecting signal SC is applied to the AND gate 48 after recovery of the precharge signal PC, the n-channel type MOS field effect transistor 36 turns on to provide the conduction path between the complementary data line 10 to the ground terminal, so that the complementary data line 10 is discharged to the ground voltage level but the data line 7 keeps the positive high voltage level. Then, a difference in voltage level appears between the data line 7 and the complementary data line 10 to form complementary voltage levels. This complementary voltage levels represent the bit of logic "1" which is read out to the data bus 21 in a similar manner to the read-out operating for the random access memory cell 1.
However, a problem is encountered in the prior-art semiconductor memory device in limitation to a bit string of a data information written in the memory cells. In detail, when the bit of logic "1" is fed from the data bus 21 to the paired data lines 7 and 10 through the input buffer circuits 45 and 44, the complementary data line 10 is in the ground voltage level. In this situation, if the read only memory cell 4 is selected by the word line 47, no substantial discharging takes place through the read only memory cell 4, so that the semiconductor memory device does not have any trouble. However, when the bit of logic "0" is supplied from the data bus 21 to the paired data lines 7 and 70, the input buffer circuit 44 causes the complementary data line 10 to go up to the positive high voltage level, so that the positive electric charges are discharged from the complementary data line 10 to a substrate (not shown) through the read only memory cell 4 in the on-state. This discharging is undesirable for the semiconductor memory device so that the data information should have the seventh bit of logic "1".